The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to methods of forming a sacrificial gate cap and self-aligned contact for a device structure, such as a field-effect transistor.
Device structures for a field-effect transistor generally include a body region, a source and a drain defined in the body region, and a gate structure configured to apply a control voltage that switches carrier flow in a channel formed in the body region. When a control voltage that is greater than a designated threshold voltage is applied, carrier flow occurs in the channel between the source and drain to produce a device output current.
Contacts may provide vertical electrical connections to features of semiconductor devices, such as the gate structure and source/drain regions of a field-effect transistor. Self-aligned contacts (SAC) are formed in contact openings that are constrained during etching by the configuration of adjacent structures, e.g., sidewall spacers on adjacent gate structures, as opposed to being constrained by a patterned resist. For example, a self-aligned contact may be formed in a contact opening that is defined by selectively etching one material, e.g., silicon dioxide, of an interlayer dielectric layer relative to other materials, such as silicon nitride sidewall spacers on adjacent gate structures.
The contacts to the source/drain regions of a field-effect transistor should remain electrically insulated from the gate electrode of the gate structure in order to ensure the functionality of the field-effect transistor. Otherwise, a short circuit can occur that may damage the field-effect transistor. In a self-aligned contact process used to contact the source/drain regions, the contact opening can partially overlap with the gate structure. To reduce the risk of shorting arising from the partial overlap, the gate electrode is protected by a cap and sidewall spacers. As technology nodes advance, the space available between adjacent gate structures decreases with decreasing pitch. The decreased spacing increases the difficulty in contacting the source/drain regions without inflicting damage to the cap and sidewall spacers protecting the gate structures when forming contact openings.
Improved methods of forming a sacrificial gate cap and self-aligned contact for a device structure are needed.